Fast self-reconfigurable embedded system on Spartan-3

Many image-processing algorithms require several stages to be processed that cannot be resolved by embedded microprocessors in a reasonable time, due to their high-computational cost. A set of dedicated coprocessors can accelerate the resolution of these algorithms, alt hough the main drawback is the area needed for their implementation. The main advantage of a reconfigurable system is that several coprocessors designed to perform different operations can be mapped on the same area in a time-multiplexed way. This work presents the architecture of an embedded system composed of a microprocessor and a run-time reconfigurable coprocessor, mapped on Spartan-3, the low-cost family of Xilinx FPGAs. Designing reconfigurable systems on Spartan-3 requires much design effort, since unlike higher cost families of Xilinx FPGAs, this device does not officially support partial reconfiguration. In order to overcome this drawback, the paper also describes the main steps used in the design flow to obtain a successful design. The main goal of the presented architecture is to reduce the coprocessor reconfiguration time, as well as accelerate image-processing algorithms. The experimental results demonstrate significant improvement in both objectives. The reconfiguration rate nearly achieves 320 Mb/s which is far superior to th e previous related works.Peer ReviewedPostprint (published version

The future roadmap of in-vehicle network processing: a HW-centric (R-)evolution

© 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The automotive industry is undergoing a deep revolution. With the race towards autonomous driving, the amount of technologies, sensors and actuators that need to be integrated in the vehicle increases exponentially. This imposes new great challenges in the vehicle electric/electronic (E/E) architecture and, especially, in the In-Vehicle Network (IVN). In this work, we analyze the evolution of IVNs, and focus on the main network processing platform integrated in them: the Gateway (GW). We derive the requirements of Network Processing Platforms that need to be fulfilled by future GW controllers focusing on two perspectives: functional requirements and structural requirements. Functional requirements refer to the functionalities that need to be delivered by these network processing platforms. Structural requirements refer to design aspects which ensure the feasibility, usability and future evolution of the design. By focusing on the Network Processing architecture, we review the available options in the state of the art, both in industry and academia. We evaluate the strengths and weaknesses of each architecture in terms of the coverage provided for the functional and structural requirements. In our analysis, we detect a gap in this area: there is currently no architecture fulfilling all the requirements of future automotive GW controllers. In light of the available network processing architectures and the current technology landscape, we identify Hardware (HW) accelerators and custom processor design as a key differentiation factor which boosts the devices performance. From our perspective, this points to a need - and a research opportunity - to explore network processing architectures with a strong HW focus, unleashing the potential of next-generation network processors and supporting the demanding requirements of future autonomous and connected vehicles.Peer ReviewedPostprint (published version

CIBERER : Spanish national network for research on rare diseases: A highly productive collaborative initiative

Altres ajuts: Instituto de Salud Carlos III (ISCIII); Ministerio de Ciencia e Innovación.CIBER (Center for Biomedical Network Research; Centro de Investigación Biomédica En Red) is a public national consortium created in 2006 under the umbrella of the Spanish National Institute of Health Carlos III (ISCIII). This innovative research structure comprises 11 different specific areas dedicated to the main public health priorities in the National Health System. CIBERER, the thematic area of CIBER focused on rare diseases (RDs) currently consists of 75 research groups belonging to universities, research centers, and hospitals of the entire country. CIBERER's mission is to be a center prioritizing and favoring collaboration and cooperation between biomedical and clinical research groups, with special emphasis on the aspects of genetic, molecular, biochemical, and cellular research of RDs. This research is the basis for providing new tools for the diagnosis and therapy of low-prevalence diseases, in line with the International Rare Diseases Research Consortium (IRDiRC) objectives, thus favoring translational research between the scientific environment of the laboratory and the clinical setting of health centers. In this article, we intend to review CIBERER's 15-year journey and summarize the main results obtained in terms of internationalization, scientific production, contributions toward the discovery of new therapies and novel genes associated to diseases, cooperation with patients' associations and many other topics related to RD research

Torre Eòlica: definició del seu envoltant mitjançant una estratègia d¿optimització aerodinàmica

[ES] Torre Eólica (La Marina de Valencia) es un proyecto de Fran Silvestre Arquitectos, concebido con la voluntad de atrapar el viento del frente marítimo, que propone un sistema de turbinas eólicas de eje vertical haciendo funcionar al edificio como un gran aerogenerador urbano. Un ejemplo estimulante, por su proximidad y carácter vanguardista, en la intersección de la aeronáutica y la arquitectura, relacionado con un contexto más amplio de acción medioambiental. Las turbinas eólicas de eje vertical se disponen en las zonas curvas que unen los núcleos de comunicación de la torre, cubiertas por una envolvente metálica calada que, siendo permeable para el viento y las vistas, confiere a la estructura un aspecto monolítico. Enmarcada en un acuerdo de colaboración con Fran Silvestre Arquitectos, la tesis de final de grado se centra en la definición de la envolvente que constituye la piel de Torre Eólica a partir de una estrategia de optimización aerodinámica. Tal experiencia de diseño multidisciplinar se desarrolla mediante un estudio fluidodinámico apoyado en simulaciones CFD, con el objetivo de determinar la geometría ideal para la envolvente en metal expandido de Torre Eólica, es decir, aquella que maximice el rendimiento de los aerogeneradores de eje vertical sin comprometer su aspecto monolítico.[EN] Torre Eólica (La Marina, València) is a project by Fran Silvestre Arquitectos, conceived by the will to trap the wind of the Mediterranean Sea, that proposes a wind turbine system of vertical axe making the tower function as a large urban renewable energy plant. A stimulant example, due to its proximity and avant-garde character, at the intersection of aeronautics and architecture, related to a wider context of environmental action. The vertical axis wind turbines are arranged in the curve areas which connect the communication cores, covered by an openwork metallic skin which being permeable to the wind together with the views confer a monolithic appearance to the structure. My final degree thesis, in the context of a collaboration agreement with Fran Silvestre Arquitectos (FSA), is centered around the definition of the envelope which becomes the skin of Torre Eólica by means of an aerodynamic optimization strategy. Such multidisciplinary design experience is developed through a fluid dynamic study supported by CFD simulations, with the aim of determining the ideal geometry for the expanded metal envelope of Torre Eólica, that is, the one that maximizes the performance of the vertical axis wind turbines without compromising its monolithic appearance.Alberola Fons, FX. (2022). Torre Eólica: definición de su envolvente mediante una estrategia de optimización aerodinámica. Universitat Politècnica de València. http://hdl.handle.net/10251/185117TFG

Sawtooth oscillations Understanding and control

Paper at 5. European Tokamak Programme Workshop Toledo (ES) 17-19 Dec 1986SIGLEAvailable from British Library Document Supply Centre- DSC:4672.262(JET-P--87/14) / BLDSC - British Library Document Supply CentreGBUnited Kingdo

Requirements on small heat meters from the viewpoint of district heating utilities

Translated from German (Fermaerme Int. 1989 v. 18(1) p. 59-60)Available from British Library Document Supply Centre- DSC:9022.0481(BG-MRS-Trans--15186)T / BLDSC - British Library Document Supply CentreSIGLEGBUnited Kingdo

Real-time embedded systems powered by FPGA dynamic partial self-reconfiguration: a case study oriented to biometric recognition applications

This work aims to pave the way for an efficient open system architecture applied to embedded electronic applications to manage the processing of computationally complex algorithms at real-time and low-cost. The target is to define a standard architecture able to enhance the performance-cost trade-off delivered by other alternatives nowadays in the market like general-purpose multi-core processors. Our approach, sustained by hardware/software (HW/SW) co-design and run-time reconfigurable computing, is synthesizable in SRAM-based programmable logic. As proof-of-concept, a run-time partially reconfigurable field-programmable gate array (FPGA) is addressed to carry out a specific application of high-demanding computational power such as an automatic fingerprint authentication system (AFAS). Biometric personal recognition is a good example of compute-intensive algorithm composed of a series of image processing tasks executed in a sequential order. In our pioneer conception, these tasks are partitioned and synthesized first in a series of coprocessors that are then instantiated and executed multiplexed in time on a partially reconfigurable region of the FPGA. The implementation benchmark of the AFAS either as a pure software approach on a PC platform under a dual-core processor (Intel Core 2 Duo T5600 at 1.83 GHz) or as a reconfigurable FPGA co-design (identical algorithm partitioned in HW/SW tasks operating at 50 or 100 MHz on the second smallest device of the Xilinx Virtex-4 LX family) highlights a speed-up of one order of magnitude in favor of the FPGA alternative. These results let point out biometric recognition as a sensible killer application for run-time reconfigurable computing, mainly in terms of efficiently balancing computational power, functional flexibility and cost. Such features, reached through partial reconfiguration, are easily portable today to a broad range of embedded applications with identical system architecture.Peer Reviewe

Flexible hardware for fingerprint image processing

Reconfigurable computing adds to the traditional hardware/software design flow a new degree of freedom in the development of electronic systems. In a system-on-chip platform, the fact that a MCU makes evolve at run-time a hardware coprocessor mapped on a FPGA, to execute thus different compute-intensive tasks in the same silicon-area, results in a clear earned value applied to the system implementation: the low-cost reached through the resources time-multiplexing. Under that approach, this work merges both reconfigurable computing and HW/SW co-design technologies to develop an efficient architecture of an automatic fingerprint authentication system (AFAS) oriented to real-time embedded applications.Peer Reviewe

Elastic gateway SoC proof of concept: experiments design and performance evaluation

© 2023 Elsevier. This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0/Mobility as we know it is rapidly changing. With the move towards autonomous and connected vehicles, the whole automotive industry is undergoing important changes faster than ever. One of the areas largely affected by these changes is the electric/electronics architecture and the in-vehicle network. This is because the number of sensors and actuators required to achieve the new goals has increased notoriously, and the exchange of information between them needs to happen in a deterministic, safe and reliable way. One of the central pieces of the new concept for vehicular networks is the gateway controller, since it is the one in charge of the exchange of information between the different elements of the network. In this work, we analyze the implications of the changes in the vehicular network architecture from the perspective of applications processing. This analysis shows the rationale behind the integration of new technologies that are required in future gateway controllers. Then, we evaluate the novel Elastic Gateway (eGW) System on Chip (SoC) as a high performance network processor that enables the integration of the wide variety of technologies required, supporting future vehicular networks. We also present the framework used to emulate the vehicular network as well as the methodology used for the deployment and validation of the Proof of Concept (PoC) for the different use cases. Finally, we demonstrate through experimental results how our PoC for eGW is able to meet the requirements of future network processing devices.Peer ReviewedPostprint (author's final draft